1. Field of the Invention
The present invention relates generally to display technologies and, more specifically, to an integrated line selection apparatus within active matrix arrays.
2. Background
Flat panel displays with electrophoretic, liquid crystal (LC), or organic light emitting diode (OLED) based pixel technology, as well as many sensor applications, all rely on a well known low temperature active matrix backplane technology to address the individual pixels in the matrix array. In an active matrix array, each pixel is controlled by one to four transistors and selection of the active gate lines in the array is typically performed using crystalline silicon Complementary Metal Oxide Semiconductor (CMOS) multiplexers and line drivers.
However, the high voltage required to drive multiple backplane transistors within the active matrix array adds to the costs of the integrated circuit. In addition, the large number of interconnects required to address the pixels in the matrix array also increase the assembly costs of the flat panel displays.
Accordingly, there is a need for a method and apparatus for efficient integration of gate line selection into the low temperature active matrix display manufacturing process in order to reduce manufacturing costs and the number of components, thus improving the reliability of the product.